Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a delay locked loop (DLL) of a semiconductor integrated circuit and a method for driving the same.
In general, semiconductor integrated circuits have been continuously improved to increase the integration degree and the operation speed thereof. A synchronous semiconductor integrated circuit has emerged, which may operate in synchronization with a source clock signal applied from the outside of the semiconductor integrated circuit in order to increase the operation speed. Such a synchronous semiconductor integrated circuit uses a DLL which generates an internal clock signal by delaying the source clock signal by a predetermined period/time so that data may be outputted accurately in synchronization with rising and falling edges of the source clock signal.
As such, the DLL generates the internal dock signal which is obtained by compensating for delay factors inside the semiconductor integrated circuit with respect to the source clock signal. This operation is referred to as locking.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the DLL 100 includes an input buffer 110, a delay line 120, a replica delay 130, a phase comparator 140, a delay controller 150, and an output buffer 160. The input buffer 110 is configured to receive and buffer a source clock signal EX_CLK and output the buffered clock signal IN_CLK. The delay line 120 is configured to delay the buffered clock signal IN_CLK in response to a control signal CTR and output an operation clock signal IN_CLK′. The replica delay 130 is configured to reflect/apply a modeled delay amount in/to the operation clock signal IN_CLK′ outputted from the delay line 120 and output a feedback clock signal FC_CLK. The modeled delay amount is a delay amount which actually occurs in input/output data paths of the system to which the DLL 100 is applied, i.e., a semiconductor integrated circuit. The phase comparator 140 is configured to compare the phase of the buffered clock signal IN_CLK outputted from the input buffer 110 with the phase of the feedback clock signal FD_CLK outputted from the replica delay 130. The delay controller 150 is configured to generate the control signal CTR in response to an output signal of the phase comparator 140. The output buffer 160 is configured to buffer the operation clock signal IN_CLK′ outputted from the delay line 120 and output an internal clock signal OUT_CLK to the outside.
While the delay line 120 controls a delay time corresponding to the delay amount reflected in the buffered clock signal IN_CLK in response to the control signal CTR, the replica delay 130 has a predetermined delay amount, that is, the modeled delay amount.
Hereafter, the operation of the DLL 100 having such a configuration is described.
When the source clock signal EX_CLK is buffered by the input buffer 110 and then transferred as the buffered clock signal IN_CLK to the delay line 120, the delay line 120 bypasses the buffered clock signal IN_CLK at first.
In such a state, the replica delay 130 receives the output signal IN_CLK′ of the delay line 120, delays the received signal by the delay time corresponding to the modeled delay amount, and outputs the feedback clock signal FD_CLK.
Then, the phase comparator 140 compares the phase of the buffered clock signal IN_CLK outputted from the input buffer 110 with the phase of the feedback clock signal FC_CLK outputted from the replica delay 130. The delay controller 150 generates the control signal CTR in response to the output signal of the phase comparator 140, and outputs the generated control signal CTR to the delay line 120.
Accordingly, the delay line 120 delays the buffered clock signal IN_CLK by the corresponding delay time in response to the control signal CTR, and outputs the delayed signal as the operation clock signal IN_CLK′.
When the above-described series of operations are repeated and the phases of the buffered clock signal IN_CLK and the feedback clock signal FC_CLK are synchronized as the comparison result of the phase comparator 140, the delay amount of the delay line 120 is locked.
Meanwhile, after the delay amount for locking the delay line 120 is decided, an update process may be performed at every period with a desired duration. Since a jitter may occur in the locked operation clock signal IN_CLK′ due to noise or the like, the above-described locking process is repetitively performed to compensate for the jitter during the update process.
However, the conventional DLL 100 has the following concerns.
Among the components composing the DLL 100, a control pulse generator (CPG), the delay line 120, and the replica delay 130 occupy most of the power consumption of the DLL 100. The CPG is not illustrated in FIG. 1. Therefore, in order to reduce the power consumption of the DLL 100, the power consumption of the CPG, the delay line 120, and the replica delay 130 needs to be reduced.
However, there is no method for reducing the power consumption in the CPG, except that flip-flops provided therein are replaced with low-power units. Since the number of delay cells provided in the delay line 120 is variable, there are difficulties in reducing the power consumption. Furthermore, since the replica delay 130 has a constant delay amount, there is no method which has been proposed to reduce the power consumption.
FIG. 2 is a graph showing the power consumption of the delay line 120 and the power consumption of the replica delay 130 with respect to a frequency of the source clock signal. Referring to FIG. 2, as the frequency of the source clock signal EX_CLK increases, the number of delay cells used in the delay line 120 decreases. Accordingly, the power consumption of the delay line 120 tends to be constant with respect to the frequency of the source clock signal. However, the power consumption of the replica delay 130 with a constant delay amount tends to increase as the frequency of the source clock signal EX_CLK increases. Therefore, it can be seen that the total power consumption of the DLL 100 also increases as the frequency of the source clock signal EX_CLK increases.
Hence, there is a demand for a DLL which is capable of adaptively optimizing the power consumption according to the frequency of the source clock signal.